1. Field of the Invention
The present invention relates to a digital-to-analog converter (referred to as xe2x80x9cD/A converterxe2x80x9d hereinafter), which is formed on a semiconductor substrate including a plurality of N-channel type MOS transistors and P-channel type MOS transistors as well and converts an input digital data into an analog voltage signal. In the following description, the plural form of the n-channel MOS transistor and the plural form of the p-channel MOS transistor will be expressed as xe2x80x9cNMOSxe2x80x2xe2x80x9d and xe2x80x9cPMOSxe2x80x2xe2x80x9d, respectively, while the single form of them will be expressed as xe2x80x9cNMOSxe2x80x9d and xe2x80x9cPMOSxe2x80x9d, respectively.
2. Prior Art
FIG. 2 is a schematic representation indicating the configuration of a prior art D/A converter of the voltage potentiometer type.
This voltage potentiometer type D/A converter is known as one of the D/A converters which are formed on the semiconductor substrate including NMOSxe2x80x2 and PMOSxe2x80x2. As shown in FIG. 2, the D/A converter 10 of the voltage potentiometer type for converting the digital data of n-bit into the analog voltage includes a decoder 11 for decoding the digital data of n-bit, and a plurality of voltage dividing resistances 12 which are connected in series with each other between the power source voltage VDD and the ground GND, each of resistances 12 being provided with a plurality of taps. The number of taps required for processing the digital data of n-bit can be expressed as 2n (n: integer). Accordingly, the taps of 1024 is needed for processing the digital data of 10-bit, for instance. Furthermore, switches of 2n i.e. 13-1, 13-2, . . . , 13-(2nxe2x88x921), and 13-(2n) are connected in parallel with each other between the voltage output node Nout and each of the taps of 2n. These switches 13-1 through 13-(2n) are selectively turned on in correspondence with the decoding result of the decoder 11 and then transmit the voltage generated at each voltage dividing resistance 12 to the node Nout.
It might be preferable to make up each of switches 13-1 through 13-(2n) of a pair of PMOS and NMOS from the point of view of suppressing the level loss to the minimum. However, this is not always preferable but rather disadvantageous from the point of view of reduction in the area of an LSI chip. For this reason, in general, the PMOS is used for transmission of the high voltage while the NMOS is used for transmission of the low voltage. Accordingly, each of switches 13-1 through 13-(2n) is made up of the PMOS or NMOS, because the PMOS is hard to transmit the low voltage while the NMOS is hard to transmit the high voltage. Furthermore, resistances 14 and 15 are connected with both ends of serial resistances 12, respectively, the resistance 14 having the function of lowering the power source voltage VDD and giving the lowered voltage to the serial voltage dividing resistance 12 and the resistance 15 having the function of raising the ground voltage and giving the raised voltage to the serial voltage dividing resistance 12. The voltage range of the node Nout is determined by these resistances 14 and 15. Each of resistances 12 is made of polycrystalline silicon (referred to as xe2x80x9cpoly-siliconxe2x80x9d hereinafter) which is hard to be influenced by the other node. All the resistances 12 are formed so as to have an equal resistive value, thereby the less distorted voltage being outputted to the node Nout.
However, the prior art D/A converter as shown in FIG. 2 included the following problems to be solved.
FIG. 3 is an illustration for showing an example of the layout with respect to the resistance group and the switch group as shown in FIG. 2.
The layout as shown in FIG. 3 is obtained by arranging, in a matrix form, a plurality of resistances 31 made of poly-silicon corresponding to the resistances 12 in FIG. 2 and a plurality of PMOSxe2x80x2 32 and NMOSxe2x80x2 33 corresponding to switches 13-1 through 13-(2n) in FIG. 2. A plurality of columns made up of PMOSxe2x80x2 32 are arranged in the region of an N-type well 34 formed on a P-type silicon substrate while a plurality of columns made up of NMOSxe2x80x2 33 are arranged directly on the P-type silicon substrate. Gates 32g of PMOSxe2x80x2 32 belonging to one column are interconnected with each other, thereby functioning as a common gate. Gates 33g of NMOSxe2x80x2 33 belonging to one column are also interconnected with each other, thereby functioning as a common gate. The column composed of resistances 31 made of poly-silicon is formed so as to intervene between adjacent columns made up of transistors (PMOSxe2x80x2 or NMOSxe2x80x2). Contacts 31a and 31b are formed such that they are connected with both ends of each resistance 31, respectively. The contact 31a of each resistance 31 and the contact 31b of the resistance 31 adjacent thereto are connected with each other through a pattern 31c. With this connection, the resistances 31 on one column of the matrix are connected in series with each other. The contact 31a of each resistance 31 is connected with the source 32a of the PMOS 32 located at the right hand of the resistance 31 or with the drain 33a of the NMOS 33 located at the same. The drain 32b of the PMOS 32 and the source 33b of the NMOS 33 are connected with a pattern 35, wherein the PMOS 32 and NMOS 33 are on the same row of the matrix and the pattern 35 is provided for every row of the matrix. In case of arranging PMOSxe2x80x2 32 and NMOSxe2x80x2 33 in the matrix form like the above, it is required for two selection switches (not shown) to be additionally provided, that is, one for selecting the gate 32g of the PMOS 32 or the gate 33g of the NMOS 33 and the other for selecting the pattern 35. Despite of the addition of these switches, there might be attained a certain advantage from the point of view of reducing the area of the LSI chip.
In case of having actually carried out this matrix arrangement, however, a step portion was created due to a very small height (thickness) difference between the region of the N-type well 34 and the P-type semiconductor substrate region other than the N-type well region. This step portion may affect the refractive index of the light. Therefore, if it is tried to make the semiconductor integrated circuit more compact, in other words, if trying to enhance the degree of integration of the semiconductor integrated circuit, the width of the finished poly-silicon i.e. the finished resistance 31 is made different depending on the place it is formed. Especially, the width of the finished resistance formed in or near the N-type well 34 is considerably made different from that of the formed outside the N-type well region 34. Difference in the width of the finished resistance 31 makes worse the frequency distortion factor caused in the D/A conversion process. For instance, if the width difference of {fraction (1/100)} is caused between finished resistances 31, it is considered in general that the frequency distortion factor would be 0.5 per cent.
In order to solve the problems as have been discussed above, according to the first aspect of the invention, there is provided a D/A converter which is formed on a semiconductor substrate including a plurality of NMOSxe2x80x2 and PMOSxe2x80x2 and converts an input digital data into an analog voltage signal. This D/A converter includes a decoder for decoding the digital data; a voltage setting resistance connecting one end thereof with a power source and outputting, from the other end thereof, a set voltage which is obtained by dropping the voltage outputted by the power source; a plurality of voltage dividing resistances connected in series with each other between the other end of the voltage setting resistance and the ground; a plurality of NMOSxe2x80x2 which are connected between a voltage output node and a plurality of taps provided on a current path made up of the voltage setting resistance and the plural voltage dividing resistances, and are selectively turned on in correspondence with the decoding result of the decoder, thereby transmitting the voltage on the connected tap to the voltage output node; and a level shift circuit shifting the voltage at the voltage output node and generating the analog voltage signal.
With adoption of such a configuration as mentioned above, it will be no longer needed to form any PMOS as a voltage dividing resistance in the N-type well region. In other words, there is no need for the voltage dividing resistance to be arranged near the boundary between the P-type semiconductor substrate and the N-type well region formed thereon, thus the voltage dividing resistance being not affected by the step portion created at the boundary and being formed having a uniform width. Accordingly, there can be realized the unification of the resistive value with respect to each of voltage dividing resistances.
Furthermore, according to the second aspect of the invention, there is provided a D/A converter formed on a semiconductor substrate including a plurality of NMOSxe2x80x2 and PMOSxe2x80x2 and having the following configuration, which includes a decoder for decoding the digital data; a voltage setting resistance connecting one end thereof with the ground and outputting, from the other end thereof, a set voltage which is obtained by raising the voltage of the ground; a plurality of voltage dividing resistances connected in series with each other between the other end of the voltage setting resistance and the power source; a plurality of PMOSxe2x80x2 which are connected between a voltage output node and a plurality of taps provided on a current path made up of the voltage setting resistance and the plural voltage dividing resistances, and are selectively turned on in correspondence with the decoding result of the decoder, thereby transmitting the voltage on the connected tap to the voltage output node; and a level shift circuit shifting the voltage at the voltage output node and generating the analog voltage signal.
With adoption of such a configuration as described above, it is made possible to make up the voltage dividing resistances by using only PMOSxe2x80x2 formed in the N-type well region, thus the condition of manufacturing the voltage dividing resistance being unified. As the result of this, there can be realized the unification of the resistive value with respect to each of voltage dividing resistances.
Still further, according to the third aspect of the invention, there is provided a D/A converter formed on a semiconductor substrate including a plurality of NMOSxe2x80x2 and PMOSxe2x80x2, and having the following configuration which includes a decoder for decoding the digital data; a plurality of the first voltage dividing resistances connected in series with each other between the power source and a mid node between the power source and the ground; a plurality of the second voltage dividing resistances connected in series with each other between the mid node and the ground; a fixed voltage supply means for supplying the fixed voltage to the mid node; a plurality of PMOSxe2x80x2 which are connected between a voltage output node and a plurality of taps provided on a current path made up of the plural first voltage dividing resistances, and are selectively turned on in correspondence with the decoding result of the decoder, thereby transmitting the voltage on the connected tap to the voltage output node; and a plurality of NMOSxe2x80x2 which are connected between the voltage output node and a plurality of taps provided on a current path made up of the plural second voltage dividing resistances, and are selectively turned on in correspondence with the decoding result of the decoder, thereby transmitting the voltage on the connected tap to the voltage output node.
With adoption of such a configuration as described above, even if the resistive value of the first voltage dividing resistance is different from that of the second voltage dividing resistance, the voltage of the mid node is fixed to the fixed voltage by the fixed voltage supply means. Consequently, the first voltage dividing resistances divide the potential difference between the power source voltage and the fixed voltage while the second voltage dividing resistances divide the potential difference between the fixed voltage and the ground voltage.